Resilient Architecture Design for Voltage Variation Vijay Janapa Reddi

ISBN: 9781608456376

Published: June 1st 2013

Paperback


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Resilient Architecture Design for Voltage Variation  by  Vijay Janapa Reddi

Resilient Architecture Design for Voltage Variation by Vijay Janapa Reddi
June 1st 2013 | Paperback | PDF, EPUB, FB2, DjVu, AUDIO, mp3, ZIP | | ISBN: 9781608456376 | 3.67 Mb

In the era of nanoscale technology scaling, we are facing the limits of physics, whereby robust and reliable microprocessor design and fabrication is becoming increasingly challenging. As technology scaling trends continue, guaranteeing correctnessMoreIn the era of nanoscale technology scaling, we are facing the limits of physics, whereby robust and reliable microprocessor design and fabrication is becoming increasingly challenging.

As technology scaling trends continue, guaranteeing correctness of execution will become prohibitively expensive and impractical. Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its operation widen worst-case timing margins of the design-degrading performance significantly.

These variations differ significantly in temporal and spatial scales. Process variations are static in nature, while voltage and temperature variations are highly sensitive to workload behavior, albeit the latter occur at very different time scales. All sources of variation affect different parts of a microprocessor die in myriad ways with complex interactions and differ in their temporal and spatial characteristics.

Microarchitectural techniques designed to mitigate parameter variations must clearly account for these differing characteristics. Traditionally, processors are designed with the worst-case operating margin, losing substantial performance.

We describe an alternate approach that researchers are exploring to design the processor for closer to nominal values. After exploring the basics of voltage variation, we describe a resilient processor architecture that couples low-overhead recovery mechanisms with microarchitectural event-guided hardware and software mechanisms to predict and eliminate the runtime penalties of voltage emergencies. Using a fail-safe hardware mechanism to tolerate voltage margin violations enables aggressive timing speculation, while the run-time hardware and software layer attempt to collaboratively smoothout future emergencies by rescheduling instructions and co-scheduling threads intelligently.

We note that voltage variation represents only one dimension of the problem. Therefore, to provide a consistent and comprehensive view of the problem we also briefly discuss the other two sources of variation where it is appropriate and required. The key techniques described in this book rely on leveraging a deep understanding about the root-cause of emergencies. Given that run-time variations like supply voltage droops and temperature fluctuations depend on the activity signature of the processor s workload, there are numerous opportunities to improve performance by dynamically adapting margins.

As you read this book, you will explore a subset of those techniques along with the power-efficiency gains that are achievable as a result of the collaborative architecture.



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